Photomask etch
for 65nm node

Critical layer masks are valuable objects because they are extremely difficult to produce and are vital to the success of any device. Emmanuel Rausa, Photomask Manager of Unaxis describes the challenges in terms of dry etch.

Today, the photomask industry produces approximately 700,000 masks per year, with 10% needing dry etch processing. However, as in many other arenas, this 10% of the market in volume is responsible for a large portion of the revenue. In the case of the mask industry, revenue generated by the most critical mask levels represents close to 45% of the total market [1]. Production of these masks is difficult and mask makers must produce bi-layer chrome levels with extremely small optical proximity correction (OPC) features and often the newer phase shift technology. From a dry etch perspective, this article will present achieved results for ~100 65nm node photomasks which were produced earlier this year.

Why use OPCs?
For high-end masks, features are of the order of the exposure wavelength. The diffraction effects cannot be ignored any longer, because they cause non-fidelity of the printed pattern on the wafer. OPCs are small features that take diffraction and optics limitations into account and help create the initially-intended design on the wafer. Figure 1 shows examples of the desired pattern with and without OPC features on the photomask and the resulting imprint on the wafer.

Mask makers review all potential printing problems and modify the mask pattern to allow the closest resemblance to the original design pattern desired on the wafer. These mask corrections are implemented by adjusting the mask pattern features during data preparation for the lithography step. The goal is to create a mask pattern that produces an image on the wafer closest to design, despite lithographic limitations. The data fracturing times can take up to 10 days! OPCs are typically small, high-resolution features that can extend mask writing times up to 30 hours. The mask then proceeds to develop, bake and finally to the dry etch process step. By this time, great amounts of resources have been invested in the mask.

Mask makers expect a lot from the final dry etch production step, because by this time most of the error budget is used up. It is understandable that the minimum possible error contribution is expected from their dry etch equipment. "Minimizing the chrome etch contribution to feature bias is required to maintain the integrity of 65nm designs that deploy aggressive Optical Proximity Correction (OPC) and narrow sub-resolution assist features (SRAFs) on the reticle." [2]

Figure 2 illustrates the use of SRAFs on a more complex circuit design. It should be noted that the use of OPC and SRAF means that the mask industry is no longer working on features 4x larger than the wafer. Minimum feature sizes on photomasks are getting close to those of features on the wafers. Future procedures will likely include automated process control (APC), which is currently being tested in wafer fabs. APC purposely adjusts some process parameters to compensate for variations in previous production steps.

The dry-etch contribution is often divided into three categories: critical dimension (CD) uniformity; average global etch bias; and feature size linearity. The uniformity requirement is evident. A mask must have consistent results for a given feature size across the entire mask. Etch bias is important because it defines the smallest clear feature possible to resolve on the mask. Finally, linearity is becoming critical because it guarantees similar etch behaviour in large features as well as the OPCs and SRAFs.

Figure 3 displays the typical dry-etch contribution achieved on a Cr mask. Results can vary depending on system configuration, pattern loading, customer specific process parameters and device type (foundry, memory or gate manufacturer). Etch performance can be tuned accordingly and Unaxis has achieved some astonishing results. For example, on memory parts, we have achieved an etch bias of 7nm with a non-uniformity of 4.4nm. For gate-level chip manufacturers' mask products, the etch bias is 13nm with a uniformity of 3nm. These are obviously 'champion' results based on highly superior lithography from some of the most sophisticated mask shops in the world.

Feature resolution demands on the wafer have now grown beyond the transfer capabilities of the best Cr masks. This has necessitated the need for a new transmissive technology in the form of what are called phase shift masks (PSM). These come in two main categories - attenuated and alternating.

Attenuation films are currently made of MoSiON. This layer 'attenuates' the light intensity going through the film introducing a phase shift of 180¡. Alternating masks are based on etching directly into the quartz substrate, inducing the phase shift. For most applications, attenuated PSMs are sufficient to achieve desired feature resolution. However, one in every thousand masks produced requires the optical properties and fixed constraints of quartz etching.

Specific challenges in etching quartz
Quartz etching has different challenges from Cr or MoSi layers. For quartz, etching occurs directly on the mask substrate. Feature sizes on the mask surfaces must be controlled, along with the etch depth of quartz features, adding a third dimension to etch control. Problems such as etch depth linearity and uniformity must be addressed. Both are important to control the phase of the light passing through the mask during wafer exposure in the stepper. In order to get the same phase change at the mask, the etch depth into the quartz substrate needs to be independent of two parameters.

First, the etch depth of the quartz for a given feature size needs to be consistent regardless of its location on the plate - commonly referred to as 'etch depth uniformity'. The etch depth of the quartz also needs to be constant across the plate for different features sizes - called 'etch depth linearity'. Etch depth linearity is a critical parameter. Generally, it is particularly difficult to get a process displaying these properties in the semiconductor industry. Reactive ion etch (RIE) lag is what this is called in the silicon industry. In lay terms, it is easily understandable: one wants to dig a consistent depth in a consistent time, regardless of the volume of material to be removed!! Of course, the quality of the trench needs to be constant. There should be straight sidewalls, no micro-trenching and no surface roughness. Unwanted features and imperfections contributed by etching are illustrated in Figure 4.

What are 65nm mask requirements?
The International Technical Roadmap for Semiconductors (ITRS) calls for a uniformity of two degrees in the quartz. This means the range of different depths in the quartz should not exceed 2nm. Given the structure of the quartz material, the etch needs to be controlled to within seven atoms. It's understandable the challenges which are presented by such a condition. First, to characterise the validity of the etch, reliable measuring at an atomic level is essential. All parameters must be controlled with optimum accuracy and though overcoming the engineering challenges is essential, most of solutions are not self-evident. Only the most rigorous methodology can bring all process parameters within range and ultimately give a production-worthy process.

On the MASK ETCHER IV, Unaxis has developed process controls that regulate etch depth uniformity. For example, Figure 5 shows how this control has allowed the uniformity to be flipped from centre fast to edge fast across different masks. Figure 6 shows that the same can be achieved with etch depth linearity. More importantly, these two process parameters are not exclusive of each other and with the proper hardware and process tuning, both results can be achieved with both good uniformity and linearity.

Knowing these processes require an ultra-clean environment and process chamber, any single particle has the potential to create a killer defect automatically making the mask useless. At Unaxis, all mask etchers are designed to prevent particle formation caused by mechanical failure over time. The production process itself is integrated and some periodic plasma cleaning is also beneficial. Most mask producers routinely check daily particle levels with specific test masks or regularly during daily production with product masks. The occurrence of a chamber opening is rare and a well protected secret because it is intrinsically related to customer production and yield.


References:
1 Dataquest, 2004.
2 TB Faure et al, "Chrome dry etching for 65nm masks manufacturing", SPIE 5567-19.